Generally, semiconductor devices have a temperature dependent characteristic. For example, in semiconductor devices comprised of Complementary Metal Oxide Semiconductor (CMOS) devices, the operational speed generally decreases as the temperature of the semiconductor device becomes high, and the consumed current generally increases as the temperature of the semiconductor device becomes low. Such a temperature characteristic may need to be considered for devices that need to perform a refresh operation, such as Dynamic Random Access Memory (DRAM) devices. Since a leakage current of a DRAM cell generally increases with an increase of the temperature of the DRAM, the time for which data is maintained may decrease. Accordingly, the timing of a refresh operation may change.
Portable electronic devices, such as pagers, cellular phones, music players, calculators, laptop computers, and PDAs, generally use direct current (DC) power. At least one battery is used as an energy source for supplying DC power. In such battery-operated systems, reducing power consumption generally is desirable. Particularly, when a battery-operated system is in a sleep mode for saving power, circuit components built in the system may be turned off. However, a DRAM installed in the system generally must continue to refresh data stored in a DRAM cell in order to preserve the DRAM cell data.
An attempt to reduce power required by a DRAM is to vary a refresh period according to a temperature of the DRAM. When a temperature area is divided into a plurality of subareas, and the refresh period is made longer (i.e., a frequency of a refresh clock is reduced) in a low temperature subarea than in other subareas, power consumption can be reduced. Hence, a temperature detector is often used to ascertain an internal temperature of a DRAM.
FIG. 1 is a circuit diagram of a conventional temperature detector 100. Referring to FIG. 1, the conventional temperature detector 100 includes a reference temperature provider 10, a plurality of branches 20, 30, and 40, PMOS transistors 51, 52, and 53, first comparators 61, 62, and 63, and second comparators 71, 72, and 73. The reference temperature provider 10 provides a reference temperature and outputs a reference temperature signal NOC0 via a comparator 60. The branches 20, 30, and 40 provide detected temperature signals. The first comparators 61, 62, and 63 compare the temperatures detected by the first, second, and third branches 20, 30, and 40 with the reference temperature to generate temperature detection signals NOC1, NOC2, and NOC3. The second comparators 71, 72, and 73 compare the reference temperature signal NOC0 with the temperature detection signals NOC1, NOC2, and NOC3, respectively, to generate output signals O1, O2, and O3, respectively. A refresh clock frequency of a DRAM can be varied in response to the output signals O1, O2, and O3 of the conventional temperature detector 100.
The temperature detector 100 provides detection temperature points set to a plurality of specific temperatures. For example, the first, second, and third branches 20, 30, and 40 may provide detection points (or trip points) of 45° C., 65° C., and 85° C., respectively. Since the temperature detector 100 may be very sensitive to a change of a semiconductor fabrication process, a temperature tuning operation may be performed in which a changed detection temperature point is tuned to a designed detection temperature point. To perform temperature trimming during the temperature tuning operation, a shifted temperature that is caused by a change of the semiconductor fabrication process generally is detected in advance.
The temperature trimming generally is performed in each of the branches 20, 30, and 40 on a wafer level. In other words, for each of the branches 20, 30, and 40 of the temperature detector 100, a search is made for a corresponding shifted temperature and a trimming operation is performed depending on the shifted temperature. Accordingly, it may take a long time to execute a trimming test. Particularly, as the number of branches used increases, the trimming test time may become longer. In addition, the branches 20, 30, and 40 may occupy a significantly large part of the entire area of a chip.